Synchronous Dynamic Random Access Memory - definizione. Che cos'è Synchronous Dynamic Random Access Memory
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Cosa (chi) è Synchronous Dynamic Random Access Memory - definizione

SDRAM FAMILY OF COMPUTER MEMORY TECHNOLOGIES
SDR SDRAM; PC100; Pc100; PC133; Pc133; SGRAM; PC66; Prefetch buffer; Virtual Channel Memory; Prefetch buffer width; VC-RAM; Vcram; SLDRAM; Sldram; SyncDRAM; Syncdram; Synchronous Graphics Random Access Memory; SDRAM; Synchronous Dynamic Random Access; Synchronous dynamic random access memory; PC100 RAM; Synchronous Dynamic Random Access Memory; SDRAM burst ordering; SDRAM burst mode; Synchronous graphics RAM; Synchronous DRAM; Synchronous graphics random-access memory; Synchronous dynamic RAM

Synchronous Dynamic Random Access Memory         
<storage> (SDRAM, Synchronous DRAM) A form of DRAM which adds a separate clock signal to the control signals. SDRAM chips can contain more complex state machines, allowing them to support "burst" access modes that clock out a series of successive bits (similar to the nibble mode DRAM). (2007-05-08)
Synchronous dynamic random-access memory         
Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.
SDRAM         
Synchronous Dynamic Random Access Memory (Reference: RAM, DRAM, IC, Intel, Samsung)

Wikipedia

Synchronous dynamic random-access memory

Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.

DRAM integrated circuits (ICs) produced from the early 1970s to early 1990s used an asynchronous interface, in which input control signals have a direct effect on internal functions only delayed by the trip across its semiconductor pathways. SDRAM has a synchronous interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by JEDEC, the clock signal controls the stepping of an internal finite-state machine that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called banks, allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an interleaved fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.

Pipelining means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.